Design Engineer chip level timing - USA Texas

Sr. Design Engineer - chip level timing * Responsible for the development, implementation, maintenance, and execution of the block-level synthesis flow.* Responsible for the development, implementation, maintenance, and execution of the chip-level timing flow.* The Sr. Design Engin.......

This position, Design Engineer chip level timing - USA Texas, was posted on February 3, 2012. Since this job has been published, it has been viewed 36 times.